The invention concerns an Integrated Circuit (IC) architecture in which individual transistors, each of which resides in a “cell,” are arranged in a matrix-like array, thereby forming a “sea” of the cells.
Groups of the cells are interconnected among themselves, by local interconnect, into functional units. (Some of these units are called “MACROS.”) The local interconnect in the units is prohibited from occupying certain layers, such as second-layer metal. The prohibited layer is used instead to connect the individual units to each other.
Several practices, common in the prior art, tend to utilize resources in integrated circuits (ICs) in an inefficient manner. These are:                1. The use of metal level 2 for local interconnect.        2. The use of metallization located above a row of transistors for interconnect for other transistors, rendering the row of transistors non-usable.        3. The use of a cell spacing (or “row pitch”) in a MACRO which is different from that of the rest of the array of standard cells into which the MACRO is embedded.        
These practices will be addressed individually.